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| Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness 期刊论文
IEICE TRANSACTIONS ON ELECTRONICS, 2017
Wang, Yuan; Lu, Guangyi; Wang, Yize; Zhang, Xing
  收藏 | 浏览/下载：3/0 | 提交时间：2017/12/03
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| Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process 期刊论文
IEICE TRANSACTIONS ON ELECTRONICS, 2016
Lu, Guangyi; Wang, Yuan; Zhang, Xing
收藏 | 浏览/下载：5/0 | 提交时间：2017/12/03
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| Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2016
Lu, Guangyi; Wang, Yuan; Zhang, Lizhong; Cao, Jian; Zhang, Xing
收藏 | 浏览/下载：3/0 | 提交时间：2017/12/03
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| A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications 其他
2016-01-01
Lu, Guangyi; Wang, Yuan; Cao, Jian; Jia, Song; Zhang, Xing
收藏 | 浏览/下载：2/0 | 提交时间：2017/12/03 |
| Transient and Static Hybrid-Triggered Active Clamp Design for Power-Rail ESD Protection 期刊论文
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016
Lu, Guangyi; Wang, Yuan; Zhang, Xing
收藏 | 浏览/下载：5/0 | 提交时间：2017/12/03
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| A Novel Low-leakage Power-rail ESD Clamp Circuit with Adjustable Triggering Voltage and Superior False-triggering Immunity for Nanoscale Applications 其他
2016-01-01
Lu, Guangyi; Wang, Yuan; Cao, Jian; Jia, Song; Zhang, Xing
收藏 | 浏览/下载：4/0 | 提交时间：2017/12/03
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| Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress 期刊论文
CHINESE PHYSICS B, 2016
Zhang, Li-Zhong; Wang, Yuan; He, Yan-Dong
收藏 | 浏览/下载：4/0 | 提交时间：2017/12/03
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| Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress 期刊论文
Chinese Physics. B, 2016
Zhang Lizhong; Wang Yuan; He Yandong
收藏 | 浏览/下载：3/0 | 提交时间：2017/12/03
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| Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress 期刊论文
Chinese Physics B, 2016
张立忠; 王源; 何燕冬
收藏 | 浏览/下载：10/0 | 提交时间：2017/12/03
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| Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process 期刊论文
Science China(Information Sciences), 2016
Guangyi LU; Yuan WANG; Lizhong ZHANG; Jian CAO; Xing ZHANG
收藏 | 浏览/下载：4/0 | 提交时间：2017/12/03
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