Design of a novel static-triggered power-rail ESD clamp circuit in a   65-nm CMOS process

doi:10.1007/s11432-015-5455-y

CORC > 北京大学 > 信息科学技术学院

	Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
	Lu, Guangyi ; Wang, Yuan ; Zhang, Lizhong ; Cao, Jian ; Zhang, Xing
刊名	SCIENCE CHINA-INFORMATION SCIENCES
	2016
关键词	electrostatic discharge (ESD) power-rail ESD clamp circuit detection mechanism transient-noise immunity false triggering transmission line pulsing (TLP) test PROTECTION DESIGN
DOI	10.1007/s11432-015-5455-y
英文摘要	This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I-leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.; National Science and Technology Major Project of China [2013ZX02303002]; SCI(E); EI; ARTICLE; wangyuan@pku.edu.cn; 12; 59
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449953]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Lu, Guangyi,Wang, Yuan,Zhang, Lizhong,et al. Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process[J]. SCIENCE CHINA-INFORMATION SCIENCES,2016.
APA	Lu, Guangyi,Wang, Yuan,Zhang, Lizhong,Cao, Jian,&Zhang, Xing.(2016).Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.SCIENCE CHINA-INFORMATION SCIENCES.
MLA	Lu, Guangyi,et al."Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process".SCIENCE CHINA-INFORMATION SCIENCES (2016).