Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD   Protection in a 65-nm CMOS Process

doi:10.1587/transele.E99.C.590

CORC > 北京大学 > 信息科学技术学院

	Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process
	Lu, Guangyi ; Wang, Yuan ; Zhang, Xing
刊名	IEICE TRANSACTIONS ON ELECTRONICS
	2016
关键词	electrostatic discharge (ESD) gate-grounded NMOS (ggNMOS) substrate-pickup stripes transmission-line-pulsing (TLP) test DEVICES PICKUP TRANSISTORS TECHNOLOGY ROBUSTNESS IMPACT
DOI	10.1587/transele.E99.C.590
英文摘要	Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS (ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are designed and fabricated in a 65-nm CMOS process. Direct current (DC), transmission-line-pulsing (TLP), human body model (HBM) and very-fast TLP (VF-TLP) tests are executed to fully characterize performance of fabricated ggNMOS. Test results reveal that an enlarged SESS parameter results in an earlier triggering behavior of ggNMOS, which presents a layout option for subtle adjustable triggering behaviors. Besides, inserted substrate-pick stripes are proved to have a bell-shape influence on the ESD robustness of ggNMOS and this bell-shape influence is valid in TLP, HBM and VF-TLP tests. Moreover, the most ESD-robust ggNMOS optimized under different inserted substrate-pick stripes always achieves a higher HBM level over the traditional ggNMOS at each concerned total device-width. Physical mechanisms of test results will be deeply discussed in this work.; National Science and Technology Major Project of China [2013ZX02303002]; SCI(E); EI; ARTICLE; wangyuan@pku.edu.cn; 5; 590-596; E99C
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/437317]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Lu, Guangyi,Wang, Yuan,Zhang, Xing. Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process[J]. IEICE TRANSACTIONS ON ELECTRONICS,2016.
APA	Lu, Guangyi,Wang, Yuan,&Zhang, Xing.(2016).Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process.IEICE TRANSACTIONS ON ELECTRONICS.
MLA	Lu, Guangyi,et al."Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process".IEICE TRANSACTIONS ON ELECTRONICS (2016).