×
验证码:
换一张
忘记密码?
记住我
CORC
首页
科研机构
检索
知识图谱
申请加入
托管服务
登录
注册
在结果中检索
科研机构
清华大学 [18]
北京大学 [8]
计算技术研究所 [3]
自动化研究所 [2]
金属研究所 [1]
苏州纳米技术与纳米仿... [1]
更多...
内容类型
期刊论文 [28]
其他 [7]
学位论文 [3]
发表日期
2017 [1]
2016 [2]
2015 [1]
2014 [3]
2013 [1]
2012 [1]
更多...
×
知识图谱
CORC
开始提交
已提交作品
待认领作品
已认领作品
未提交全文
收藏管理
QQ客服
官方微博
反馈留言
浏览/检索结果:
共38条,第1-10条
帮助
已选(
0
)
清除
条数/页:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
排序方式:
请选择
作者升序
作者降序
题名升序
题名降序
发表日期升序
发表日期降序
提交时间升序
提交时间降序
Swarm Intelligence-Inspired Spontaneous Fabrication of Optimal Interconnect at the Micro/Nanoscale
期刊论文
ADVANCED MATERIALS, 2017, 卷号: 29, 期号: 7
作者:
Su, Meng
;
Huang, Zhandong
;
Huang, Yong
;
Chen, Shuoran
;
Qian, Xin
收藏
  |  
浏览/下载:23/0
  |  
提交时间:2019/04/09
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586
作者:
Chen, Shuai
;
Li, Hao
;
Chiang, Patrick Yin
收藏
  |  
浏览/下载:21/0
  |  
提交时间:2019/12/13
All-digital clock and data recovery (ADCDR)
delay-locked loop (DLL)
forwarded-clock (FC) receiver
high-density interconnect
jitter tolerance
multicore processor
process variation
voltage and temperature drift
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2
作者:
Chen, Shuai
;
Li, Hao
;
Chiang, Patrick Yin
收藏
  |  
浏览/下载:5/0
  |  
提交时间:2019/12/13
All-digital clock and data recovery (ADCDR)
delay-locked loop (DLL)
forwarded-clock (FC) receiver
high-density interconnect
jitter tolerance
multicore processor
process variation
voltage and temperature drift
Interconnect delay optimization for deep submicron technology
期刊论文
Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2015, 卷号: Vol.42 No.4, 页码: 85-92
作者:
Li, Ren-Fa
;
Xu, Shi
;
Zhao, Zhen-Yu
;
Wang, Yao
;
Liu, Chang
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2019/12/31
Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes
期刊论文
NANOSCALE, 2014, 卷号: 6, 期号: 24, 页码: 14891-14897
作者:
Gu, WB (顾唯兵)
;
Cui, Z (崔铮)
收藏
  |  
浏览/下载:31/0
  |  
提交时间:2015/02/03
LIGHT
FABRICATION
OXIDE
Statistical Assessment Methodology for the Design and Optimization of Cross-Point RRAM Arrays
其他
2014-01-01
Li, Haitong
;
Jiang, Zizhen
;
Huang, Peng
;
Chen, Hong-Yu
;
Chen, Bing
;
Liu, Rui
;
Chen, Zhe
;
Zhang, Feifei
;
Liu, Lifeng
;
Gao, Bin
;
Liu, Xiaoyan
;
Yu, Shimeng
;
Wong, H.S. Philip
;
Kang, Jinfeng
收藏
  |  
浏览/下载:5/0
  |  
提交时间:2015/11/13
Resistive random access memory (RRAM)
variation
cross-point array
statistical assessment
optimization
A comprehensive speed-power analysis of resistive switching memory arrays with selection devices
其他
2014-01-01
Li, Haitong
;
Huang, Peng
;
Chen, Zhe
;
Chen, Bing
;
Gao, Bin
;
Liu, Lifeng
;
Liu, Xiaoyan
;
Kang, Jinfeng
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2015/11/13
Preliminary validation of entransy-based thermal management for 3D IC
其他
2013-01-01
Pi, Yudan
;
Sun, Han
;
Huang, Jie
;
Wang, Wei
;
Chen, Jing
;
Jin, Yufeng
;
Cao, Bingyang
收藏
  |  
浏览/下载:3/0
  |  
提交时间:2015/11/13
3D IC
thermal management
entransy
optimal parameter
HEAT-TRANSFER
THE INVESTIGATION OF 3D EMBEDDED MICROCHANNEL NETWORKS FOR 3D IC COOLING, VACUUM PACKAGING AND THZ PASSIVE DEVICE APPLICATIONS
其他
2012-01-01
Miao, Min
;
Zhang, Jing
;
Zhang, Yang
;
Han, Bo
;
Jin, Yufeng
收藏
  |  
浏览/下载:4/0
  |  
提交时间:2015/11/16
CIRCUITS
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects
期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 10, 页码: 1787-1800
作者:
Zhang, Ying
;
Li, Huawei
;
Min, Yinghua
;
Li, Xiaowei
收藏
  |  
浏览/下载:10/0
  |  
提交时间:2019/12/16
Crosstalk
crosstalk tolerance
interconnects
network-on-chip (NOC)
©版权所有 ©2017 CSpace - Powered by
CSpace