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Optimization of AVS plus Software Decoder for High-definition Video 会议论文
8th International Conference on Internet Multimedia Computing and Service (ICIMCS), Xidian Univ, State Key Lab Integrated Serv Networks, Xian, PEOPLES R CHINA, 2016-08-19
作者:  Chen, Peijuan;  Liu, Rongke;  Pan, Yu;  Du, Qiuchen;  Lin, Manqing
收藏  |  浏览/下载：5/0  |  提交时间：2019/12/30
太阳望远镜海量数据并行处理技术研究 学位论文
博士, 北京: 中国科学院研究生院, 2015
作者:  李雪宝
收藏  |  浏览/下载：100/0  |  提交时间：2016/05/25
MrPhi: An Optimized MapReduce Framework on Intel Xeon Phi Coprocessors 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2015
Lu, Mian; Liang, Yun; Huynh Phung Huynh; Ong, Zhongliang; He, Bingsheng; Goh, Rick Siow Mong
收藏  |  浏览/下载：4/0  |  提交时间：2017/12/03
Communication-oriented performance optimisation during code generation from simulink models 期刊论文
International Journal of Embedded Systems, 2014, 卷号: 6, 期号: 2-3, 页码: 124-134
作者:  Yan, Rongjie;  Yu, Min;  Huang, Kai;  Zhang, Xiaomeng
收藏  |  浏览/下载：23/0  |  提交时间：2014/12/16
THCAS:内容存储系统及其性能优化 期刊论文
2010, 2010
宋铭; 刘川意; 张悠慧; 汪东升; SONG Ming; LIU Chuanyi; ZHANG Youhui; WANG Dongsheng
收藏  |  浏览/下载：1/0
基于内容存储系统及其性能优化 期刊论文
2010, 2010
宋铭; 刘川意; 张悠慧; 汪东升; SONG Ming; LIU Chuanyi; ZHANG Youhui; WANG Dongsheng
收藏  |  浏览/下载：2/0
Prophet+: An extended multicore simulator for speculative multithreading 期刊论文
Hsi-An Chiao Tung Ta Hsueh/Journal of Xi'an Jiaotong University, 2010, 卷号: 44, 期号: [db:dc_citation_issue]
作者:  Song, Shaolong;  Zhao, Yinliang;  Feng, Boqin;  Wei, Yuanke;  Wang, Xuhao
收藏  |  浏览/下载：2/0  |  提交时间：2019/12/10
Real-time video compressing under DSP/BIOS (EI CONFERENCE) 会议论文
MIPPR 2009 - Medical Imaging, Parallel Processing of Images, and Optimization Techniques: 6th International Symposium on Multispectral Image Processing and Pattern Recognition, October 30, 2009 - November 1, 2009, Yichang, China
Chen Q.-P.; Li G.-J.
收藏  |  浏览/下载：18/0  |  提交时间：2013/03/25
This paper presents real-time MPEG-4 Simple Profile video compressing based on the DSP processor. The programming framework of video compressing is constructed using TMS320C6416 Microprocessor  the architecture level optimizations are used to improve software pipeline. The system used DSP/BIOS to realize multi-thread scheduling. The whole system realizes high speed transition of a great deal of data. Experimental results show the encoder can realize real-time encoding of 768*576  TDS510 simulator and PC. It uses embedded real-time operating system DSP/BIOS and the API functions to build periodic function  25 frame/s video images. 2009 Copyright SPIE - The International Society for Optical Engineering.  tasks and interruptions etcs. Realize real-time video compressing. To the questions of data transferring among the system. Based on the architecture of the C64x DSP  utilized double buffer switched and EDMA data transfer controller to transit data from external memory to internal  and realize data transition and processing at the same time  

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