CORC

浏览/检索结果: 共1条,第1-1条 帮助

限定条件                    
已选(0)清除 条数/页:   排序方式:
The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文
2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China
Jiang L.-F.; Wang W.-G.
收藏  |  浏览/下载:29/0  |  提交时间:2013/03/25
In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to  counting circuit  the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE.  we design a circuit based on FPGA to realize multiplier  kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering  multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder  at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last  timing simulation based on Modelsim carried on the three modules  


©版权所有 ©2017 CSpace - Powered by CSpace