SEU Mitigation Strategies for SRAM-based FPGA

	SEU Mitigation Strategies for SRAM-based FPGA
	Luo Pei; Zhang Jian
	2011
会议名称	International Symposium on Photoelectronic Detection and Imaging 2011 - Space Exploration Technologies and Applications
会议日期	MAY 24-26, 2011
会议地点	Beijing, PEOPLES R CHINA
关键词	SRAM-based FPGA SEU scrub reliability
页码	81960N
通讯作者	Luo, P (reprint author), Chinese Acad Sci, Lab Integrated Space Elect Technol, Ctr Space Sci & Applicat Res, Beijing 100190, Peoples R China.
中文摘要	The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.
英文摘要	The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.
收录类别	CPCI
会议主办者	Photoelect Technol Profess Comm, CSA, Tianjin Jinhang Inst Tech Phys, CASIC, Sci & Technol Low Light Level Night Vis Lab, Chinese Soc Astronaut
会议录	INTERNATIONAL SYMPOSIUM ON PHOTOELECTRONIC DETECTION AND IMAGING 2011: SPACE EXPLORATION TECHNOLOGIES AND APPLICATIONS
会议录出版者	SPIE-INT SOC OPTICAL ENGINEERING
会议录出版地	BELLINGHAM
学科主题	空间技术
语种	英语
ISSN号	0277-786X
ISBN号	978-0-81948-837-4
内容类型	会议论文
源URL	[http://ir.nssc.ac.cn/handle/122/2950]
专题	国家空间科学中心_空间技术部
推荐引用方式 GB/T 7714	Luo Pei,Zhang Jian. SEU Mitigation Strategies for SRAM-based FPGA[C]. 见:International Symposium on Photoelectronic Detection and Imaging 2011 - Space Exploration Technologies and Applications. Beijing, PEOPLES R CHINA. MAY 24-26, 2011.