Compact Model for Double-Gate Tunnel FETs with Gate-Drain Underlap

doi:10.1109/TED.2017.2762861

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	Compact Model for Double-Gate Tunnel FETs with Gate-Drain Underlap
	Xu, Peng 1; Lou, Haijun 1,2; Zhang, Lining 3; Yu, Zhonghua 1; Lin, Xinnan 1
刊名	IEEE Transactions on Electron Devices
	2017-12-01
卷号	64 期号:12 页码:5242-5248
关键词	Capacitance SPICE Tunnel field effect transistors Ambipolar currents Compact model Double gate tunnel fets Doublegate tunnel fets (DG-TFET) Effective resistances Electrical characteristic Gate drain Tunneling field-effect transistors
ISSN号	00189383
DOI	10.1109/TED.2017.2762861
英文摘要	A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C dg) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developed which enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem. © 1963-2012 IEEE.
资助项目	General Research Fund from the Research Grant Council of Hong Kong[611012]
WOS研究方向	Engineering ; Physics
语种	英语
出版者	Institute of Electrical and Electronics Engineers Inc.
WOS记录号	WOS:000417727500062
状态	已发表
内容类型	期刊论文
源URL	[http://ir.lut.edu.cn/handle/2XXMBERH/114971]
专题	兰州理工大学
通讯作者	Lou, Haijun; Lin, Xinnan
作者单位	1.Peking Univ, Shenzhen Key Lab Adv Electron Device & Integrat, Sch Elect & Comp Engn, Shenzhen Grad Sch, Shenzhen 518055, Peoples R China 2.Lanzhou Univ Technol, Sch Sci, Lanzhou 730050, Gansu, Peoples R China 3.Shenzhen Univ, Coll Elect Sci & Technol, Shenzhen 518060, Peoples R China
推荐引用方式 GB/T 7714	Xu, Peng,Lou, Haijun,Zhang, Lining,et al. Compact Model for Double-Gate Tunnel FETs with Gate-Drain Underlap[J]. IEEE Transactions on Electron Devices,2017,64(12):5242-5248.
APA	Xu, Peng,Lou, Haijun,Zhang, Lining,Yu, Zhonghua,&Lin, Xinnan.(2017).Compact Model for Double-Gate Tunnel FETs with Gate-Drain Underlap.IEEE Transactions on Electron Devices,64(12),5242-5248.
MLA	Xu, Peng,et al."Compact Model for Double-Gate Tunnel FETs with Gate-Drain Underlap".IEEE Transactions on Electron Devices 64.12(2017):5242-5248.