Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction | |
Hongjuan Wang ; Genquan Han ; Member,IEEE ; Xiangwei Jiang ; Member,IEEE ; Yan Liu ; Jincheng Zhang; Yue Hao; Senior Member,IEEE | |
刊名 | IEEE TRANSACTIONS ON ELECTRON DEVICES |
2019 | |
卷号 | 66期号:4页码:1985-1989 |
内容类型 | 期刊论文 |
源URL | [http://ir.semi.ac.cn/handle/172111/29411] |
专题 | 半导体研究所_半导体超晶格国家重点实验室 |
推荐引用方式 GB/T 7714 | Hongjuan Wang ; Genquan Han ; Member,IEEE ; Xiangwei Jiang ; Member,IEEE ; Yan Liu ; Jincheng Zhang; Yue Hao; Senior Member,IEEE. Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES,2019,66(4):1985-1989. |
APA | Hongjuan Wang ; Genquan Han ; Member,IEEE ; Xiangwei Jiang ; Member,IEEE ; Yan Liu ; Jincheng Zhang; Yue Hao; Senior Member,IEEE.(2019).Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction.IEEE TRANSACTIONS ON ELECTRON DEVICES,66(4),1985-1989. |
MLA | Hongjuan Wang ; Genquan Han ; Member,IEEE ; Xiangwei Jiang ; Member,IEEE ; Yan Liu ; Jincheng Zhang; Yue Hao; Senior Member,IEEE."Improved Performance in GeSn/SiGeSn TFET by Hetero-Line Architecture With Staggered Tunneling Junction".IEEE TRANSACTIONS ON ELECTRON DEVICES 66.4(2019):1985-1989. |
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