A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps

	A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps
	Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian
刊名	SENSORS
	2021
卷号	21 期号:18 页码:6006
公开日期	2021
内容类型	期刊论文
源URL	[http://ir.semi.ac.cn/handle/172111/30795]
专题	半导体研究所_半导体超晶格国家重点实验室
推荐引用方式 GB/T 7714	Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian. A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps[J]. SENSORS,2021,21(18):6006.
APA	Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian.(2021).A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.SENSORS,21(18),6006.
MLA	Zhang, Ling; Yang, Jing; Shi, Cong; Lin, Yingcheng; He, Wei; Zhou, Xichuan; Yang, Xu; Liu, Liyuan; Wu, Nanjian."A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps".SENSORS 21.18(2021):6006.