Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

doi:10.1007/s41365-021-00979-8

	Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies
	He, Ze 1,3; Zhao, Shi-Wei 1,3; Liu, Tian-Qi 2; Cai, Chang 1,3; Yan, Xiao-Yu 1,3; Gao, Shuai 1,3; Liu, Yu-Zhu 1,3; Liu, Jie 1,3
刊名	NUCLEAR SCIENCE AND TECHNIQUES
	2021-12-01
卷号	32 期号:12 页码:13
关键词	Double interlocked storage cell (DICE) Error detection and correction (EDAC) code Heavy ion Radiation hardening technology Single event upset (SEU) Static random-access memory (SRAM)
ISSN号	1001-8042
DOI	10.1007/s41365-021-00979-8
通讯作者	Liu, Tian-Qi(liutianqi@mail.tsinghua.edu.cn) ; Liu, Jie(j.liu@impcas.ac.cn)
英文摘要	A dual double interlocked storage cell (DICE) interleaving layout static random-access memory (SRAM) is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology. The single event upset (SEU) cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer (LET) value ranging from 1.7 to 83.4 MeV/(mg/cm(2)). Experimental results show that the upset threshold (LETth) of a 4 KB block is approximately 6 MeV/(mg/cm(2)), which is much better than that of a standard unhardened SRAM with an identical technology node. A 1 KB block has a higher LETth of 25 MeV/(mg/cm(2)) owing to the use of the error detection and correction (EDAC) code. For a Ta ion irradiation test with the highest LET value (83.4 MeV/(mg/cm(2))), the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably. Compared with normal incident ions, the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test. Moreover, the SEU cross section indicates a significant dependence on the data pattern. When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell, it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout. Finally, some suggestions are provided to further improve the radiation resistance of the memory. By implementing a particular design at the layout level, the SEU tolerance of the memory is improved significantly at a low area cost. Therefore, the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.
资助项目	National Natural Science Foundation of China[12035019] ; National Natural Science Foundation of China[11690041] ; National Natural Science Foundation of China[11805244]
WOS关键词	SINGLE EVENT UPSETS ; FLIP-FLOP ; CMOS SRAM ; AREA-EFFICIENT ; MEMORY CELL ; DESIGN ; ROBUST ; CHARGE ; SENSITIVITY ; COLLECTION
WOS研究方向	Nuclear Science & Technology ; Physics
语种	英语
出版者	SPRINGER SINGAPORE PTE LTD
WOS记录号	WOS:000729785400001
资助机构	National Natural Science Foundation of China
内容类型	期刊论文
源URL	[http://119.78.100.186/handle/113462/140120]
专题	中国科学院近代物理研究所
通讯作者	Liu, Tian-Qi; Liu, Jie
作者单位	1.Chinese Acad Sci, Inst Modern Phys, Lanzhou 730000, Peoples R China 2.Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China 3.Univ Chinese Acad Sci, Sch Nucl Sci & Technol, Beijing 100049, Peoples R China
推荐引用方式 GB/T 7714	He, Ze,Zhao, Shi-Wei,Liu, Tian-Qi,et al. Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies[J]. NUCLEAR SCIENCE AND TECHNIQUES,2021,32(12):13.
APA	He, Ze.,Zhao, Shi-Wei.,Liu, Tian-Qi.,Cai, Chang.,Yan, Xiao-Yu.,...&Liu, Jie.(2021).Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies.NUCLEAR SCIENCE AND TECHNIQUES,32(12),13.
MLA	He, Ze,et al."Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies".NUCLEAR SCIENCE AND TECHNIQUES 32.12(2021):13.