An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS | |
Yin, S.; Ouyang, P.; Yang, J.; Lu, T.; Li, X.; Liu, L.; Wei, S. | |
2018 | |
会议名称 | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
关键词 | CMOS integrated circuits Deep neural networks Metadata VLSI circuits 28nm CMOS Data reconstruction Energy efficient Load-balancing mechanisms Reconfigurable processors State of the art Ultra-high energies Energy efficiency |
卷号 | 2018-June |
页码 | 37-38 |
URL标识 | 查看原文 |
内容类型 | 会议论文 |
URI标识 | http://www.corc.org.cn/handle/1471x/5929070 |
专题 | 北京航空航天大学 |
推荐引用方式 GB/T 7714 | Yin, S.,Ouyang, P.,Yang, J.,et al. An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS[C]. 见:IEEE Symposium on VLSI Circuits, Digest of Technical Papers. |
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