Hardware architecture for AVS entropy encoder

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	Hardware architecture for AVS entropy encoder
	Xu, Long 1; Deng, Lei 2; Ji, Xiangyang 1; Peng, Xiaoming 2; Gao, Wen 1
刊名	IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
	2008-05-01
卷号	54 期号:2 页码:769-777
关键词	AVS-P2 entropy coding VLC context-based hardware pipeline
ISSN号	0098-3063
英文摘要	In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know, such the serial run-length method is usually undesirable for hardware accelerator and thus, this paper proposes an efficient parallel algorithm to Run-Length Coding, which can determine the (Run, Level) combinations for one row of coefficients from a block in one clock cycle. In addition, Level-based multiple VLC tables switch mechanism (Context-based VLC) is further introduced in AVS-P2 entropy coding module to identify the big variation of probability distribution of (Run, Level) combinations. As a result, table selection for coding the current Level necessarily depends on the previously coded coefficients. Thus, we propose a parallel Looking-Up Table method, which can select the tables for one row of coefficients from a block in one clock cycle. On the other band, at RDO stage, the calculation of rate term only needs to get the number of bits for each coded signal without the knowledge of its concrete value. Consequently, in hardware design, the Looking-Up Table in pre-coding can be mapped into a series of logic operations and thus much hardware memory can be saved. At the actual entropy coding, we only need to replace the logic operation of pre-coding with the actual 2D-VLC tables. Using our proposed hardware accelerator of A VS entropy coder, the results of simulation and synthesis demonstrate that the computing complexity and memory requirements are both reduced.
WOS研究方向	Engineering ; Telecommunications
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000257285300085
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/11251]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Xu, Long
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China 2.Peking Univ, Inst Digital Media, Sch Elect Engn & Comp Sci, Beijing 100871, Peoples R China
推荐引用方式 GB/T 7714	Xu, Long,Deng, Lei,Ji, Xiangyang,et al. Hardware architecture for AVS entropy encoder[J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,2008,54(2):769-777.
APA	Xu, Long,Deng, Lei,Ji, Xiangyang,Peng, Xiaoming,&Gao, Wen.(2008).Hardware architecture for AVS entropy encoder.IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,54(2),769-777.
MLA	Xu, Long,et al."Hardware architecture for AVS entropy encoder".IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 54.2(2008):769-777.