An Accelerator for High Efficient Vision Processing

doi:10.1109/TCAD.2016.2584062

CORC > 计算技术研究所 > 中国科学院计算技术研究所 > 中国科学院计算技术研究所期刊论文 > 英文

	An Accelerator for High Efficient Vision Processing
	Du, Zidong 3,4; Liu, Shaoli 3; Fasthuber, Robert 5; Chen, Tianshi 3; Ienne, Paolo 5; Li, Ling 3; Luo, Tao 3,4; Guo, Qi 3; Feng, Xiaobing 3; Chen, Yunji 2,3
刊名	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
	2017-02-01
卷号	36 期号:2 页码:227-240
关键词	Accelerator architectures convolutional neural network vision sensor
ISSN号	0278-0070
DOI	10.1109/TCAD.2016.2584062
英文摘要	In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are convolutional neural networks (CNNs), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is highly energy-efficient. We present a single-core implementation down to the layout at 65 nm, with a modest footprint of 5.94mm(2) and consuming only 336mm(2), but still about 30x faster than high-end GPUs. For visual processing with higher resolution and frame-rate requirements, we further present a multicore implementation with elevated performance.
资助项目	NSF of China[61133004] ; NSF of China[61303158] ; NSF of China[61432016] ; NSF of China[61472396] ; NSF of China[61473275] ; NSF of China[61522211] ; NSF of China[61532016] ; NSF of China[61521092] ; 973 Program of China[XDA06010403] ; 973 Program of China[XDB02040009] ; International Collaboration Key Program of the CAS[171111KYSB20130002] ; 10000 talent program
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000394682200003
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/7507]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Du, Zidong
作者单位	1.INRIA, F-91120 Palaiseau, France 2.Chinese Acad Sci, CAS Ctr Excellence Brain Sci, Beijing 100190, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 4.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 5.Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland
推荐引用方式 GB/T 7714	Du, Zidong,Liu, Shaoli,Fasthuber, Robert,et al. An Accelerator for High Efficient Vision Processing[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2017,36(2):227-240.
APA	Du, Zidong.,Liu, Shaoli.,Fasthuber, Robert.,Chen, Tianshi.,Ienne, Paolo.,...&Temam, Olivier.(2017).An Accelerator for High Efficient Vision Processing.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,36(2),227-240.
MLA	Du, Zidong,et al."An Accelerator for High Efficient Vision Processing".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 36.2(2017):227-240.