Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs

doi:10.1109/TVLSI.2017.2707120

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	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs
	Lu, Weina 1,2; Hu, Yu 1,2; Ye, Jing 1; Li, Xiaowei 1,2
刊名	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
	2017-09-01
卷号	25 期号:9 页码:2525-2537
关键词	Computer-aided design flow field-programmable gate arrays (FPGAs) hotspot optimization performance
ISSN号	1063-8210
DOI	10.1109/TVLSI.2017.2707120
英文摘要	The continuous shrinking of the feature size in CMOS technology has significantly increased the power densities of integrated circuits, leading to severe temperature issues. However, the previous offline simulation-based thermal optimization works cast large deviations with the reality, while online sensing-based thermal managements usually incur significant performance overhead. Therefore, it is crucial to propose a method that could achieve fine-grained optimization with accurate temperature profiles. In this paper, we propose a timingconstraint temperature sensing-based hotspot-driven placement technique for field-programmable gate arrays (FPGAs). The hotspot optimization issue is modeled as a hyper minimum bipartite matching problem and is solved by a place adjustment with the input of an online sensed temperature profile. We propose an open-source/commercial hybrid design flow to implement the whole optimization in Xilinx Virtex-6 FPGA. Experimental results demonstrate a significant reduction in peak temperature and a great improvement on thermal uniformity, with slight performance overhead under timing constraints.
资助项目	National Natural Science Foundation of China[61274030] ; National Natural Science Foundation of China[61532017] ; National Natural Science Foundation of China[61376043] ; National Natural Science Foundation of China[61521092]
WOS研究方向	Computer Science ; Engineering
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
WOS记录号	WOS:000408425400013
内容类型	期刊论文
源URL	[http://119.78.100.204/handle/2XEOYT63/6668]
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Hu, Yu
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Chinese Acad Sci, Grad Univ, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Lu, Weina,Hu, Yu,Ye, Jing,et al. Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25(9):2525-2537.
APA	Lu, Weina,Hu, Yu,Ye, Jing,&Li, Xiaowei.(2017).Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25(9),2525-2537.
MLA	Lu, Weina,et al."Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25.9(2017):2525-2537.