Design and Implementation of Parameterized Convolutional encoder IP cores

CORC > 沈阳自动化研究所 > 中国科学院沈阳自动化研究所 > 工业控制网络与系统研究室

	Design and Implementation of Parameterized Convolutional encoder IP cores
	Duan MQ(段茂强); Huang XL(黄晓莉)
	2012
会议名称	The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
会议日期	October 16-18, 2012
会议地点	Zhoushan,China
关键词	convolutional encodes parallel computing parameterized IP core
页码	1455-1458
中文摘要	The parameterized IP (Intellectual Property) core is flexible reused in the SoC (system on chip) development project, reduce the development period and occupy the appreciate market. The convolutional coder is a kind of good channel code, which is widely used in many fields such as deep space telecommunication, wireless communication and so on. In this paper, we design and implement general parameterized IP cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption.
产权排序	1
会议主办者	IEEE
会议录	The 2nd International Conference on Electronics,Communications and Control (ICECC2012)
会议录出版者	IEEE Computer Society
会议录出版地	New York, USA
语种	英语
ISBN号	978-0-7695-4806-7
内容类型	会议论文
源URL	[http://ir.sia.cn/handle/173321/10236]
专题	沈阳自动化研究所_工业控制网络与系统研究室
推荐引用方式 GB/T 7714	Duan MQ,Huang XL. Design and Implementation of Parameterized Convolutional encoder IP cores[C]. 见:The 2nd International Conference on Electronics,Communications and Control (ICECC2012). Zhoushan,China. October 16-18, 2012.