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	Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead
	Zhang, Zhiyong; Ju, Lei; Jia, Zhiping
刊名	Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
	2016
页码	942-947
会议名称	19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
URL标识	查看原文
会议日期	14 March 2016 through 18 March 2016
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/4708290
专题	山东大学
作者单位	School of Computer Science and Technology, Shandong University, Jinan, China
推荐引用方式 GB/T 7714	Zhang, Zhiyong,Ju, Lei,Jia, Zhiping. Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead[J]. Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016,2016:942-947.
APA	Zhang, Zhiyong,Ju, Lei,&Jia, Zhiping.(2016).Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead.Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016,942-947.
MLA	Zhang, Zhiyong,et al."Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead".Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 (2016):942-947.

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