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	An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars
	Yang, Dong[1,2]; Hu, Shengdong[1,2,3]; Lei, Jianmei[3]; Huang, Ye[1,2]; Yuan, Qi[1,2]; Jiang, Yuyu[1,2]; Guo, Jingwei[1,2]; Cheng, Kun[1,2]; Lin, Zhi[1,2]; Zhou, Xichuan[1,2]
	2017
卷号	112页码:269-278
URL标识	查看原文
内容类型	期刊论文
URI标识	http://www.corc.org.cn/handle/1471x/2977608
专题	重庆大学
推荐引用方式 GB/T 7714	Yang, Dong[1,2],Hu, Shengdong[1,2,3],Lei, Jianmei[3],et al. An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars[J],2017,112:269-278.
APA	Yang, Dong[1,2].,Hu, Shengdong[1,2,3].,Lei, Jianmei[3].,Huang, Ye[1,2].,Yuan, Qi[1,2].,...&Tang, Fang[1,2].(2017).An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars.,112,269-278.
MLA	Yang, Dong[1,2],et al."An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars".112(2017):269-278.

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