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	A PVT variation tolerant and low power 5Gbs clock and data recovery circuit for PCI-E 2.0USB 3.0
	Zhang F(张锋); Chen CY(陈铖颖)
	2016-01-28
英文摘要	An all-digital on-chip clock generator is proposed in this paper. It features the tolerance of process, voltage and temperature variation according to the special algorithm. The clock generator depends on CMOS standard delay cell without any external clock source, and the periods of CMOS standard delay cell are calculated by the linear polynomial fitting. The proposed on-chip clock generator has been implemented in 180 nm CMOS. The output clock is 10MHz~40MHz adjustable.
文献子类	会议论文
内容类型	会议论文
源URL	[http://159.226.55.106/handle/172511/16304]
专题	微电子研究所_智能感知研发中心
推荐引用方式 GB/T 7714	Zhang F,Chen CY. A PVT variation tolerant and low power 5Gbs clock and data recovery circuit for PCI-E 2.0USB 3.0[C]. 见:.

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