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	Optimization Design of a Low Power Asynchronous DES for Security Applications Based on Balsa and Synchronous Tools
	Zhang, Qihui ; Cao, Jian ; Cao, Xixin ; Zhang, Xing ; Ye, Yin ; Zhao, Yanguang ; Chen, Botao
	2015
关键词	asynchronous DES low power Balsa properties optimization schemes ASIC FPGA dual-rail security applications
英文摘要	DES has been widely used in current financial security application, but side-channel attacks are considered as serious threats to DES cryptographic algorithm. Asynchronous DES design will be a proper solution because of its natural properties. First, a low power asynchronous DES architecture and sub key generation architecture are proposed. Then, optimized Balsa implementation, GTECH-based implementation and black-box-based implementation are described to reduce area and power. Furthermore, a dual-rail implementation is carried out for future security applications and a Spartan-6 FPGA verification is checked before taping out. ASIC implementation results show that our proposed asynchronous DES architecture and black-box-based scheme can achieve about 20% lower power with 25% area increase of its synchronous equivalent, and its energy is only 8.2% and 27.3% of those reported in other papers, respectively. FPGA experimental results show that our proposed asynchronous DES exhibits an operation frequency of 196.2 MHz and costs only 4% slice LUTs. Moreover, it can be suitably integrated into contactless smart cards.; CPCI-S(ISTP); caojian@ss.pku.edu.cn; zhaoyg@hed.com.cn; 124-129
语种	英语
出处	International conference on electronics, communications and computers
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/450347]
专题	软件与微电子学院
推荐引用方式 GB/T 7714	Zhang, Qihui,Cao, Jian,Cao, Xixin,et al. Optimization Design of a Low Power Asynchronous DES for Security Applications Based on Balsa and Synchronous Tools. 2015-01-01.

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