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	A Low-Power Calibration-Free Fractional-N Digital PLL with High Linear Phase Interpolator
	Yang, Fan ; Guo, Hangyan ; Wang, Runhua ; Zhang, Zherui ; Liu, Junhua ; Liao, Huailin
	2016
关键词	Calibration-free Digital PLL Fractional-N Glitch-free Harmonic Rejection Phase Interpolator
英文摘要	This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower architecture complexity and minimal design effort. A high frequency resolution digitally-controlled oscillator with an equivalent variable inductor is also utilized. A 2.2-GHz digital PLL has been implemented in a 55-nm CMOS technology. The frequency resolution of DCO is 1.58 kHz, and in-band phase noise of PLL is -104.4 dBc/Hz. The PLL consumes 2.43 mA from a 1.2-V supply voltage and occupies an active area of 0.216 mm(2).; Beijing Natural Foundation [4151002]; National Natural Science Foundation of China [61574008]; CPCI-S(ISTP); 269-272
语种	英语
出处	IEEE Asian Solid-State Circuits Conference (A-SSCC)
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/470231]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yang, Fan,Guo, Hangyan,Wang, Runhua,et al. A Low-Power Calibration-Free Fractional-N Digital PLL with High Linear Phase Interpolator. 2016-01-01.

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