Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness

doi:10.1143/JJAP.48.04C052

CORC > 北京大学 > 信息科学技术学院

	Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness
	Yu, Shimeng ; Zhao, Yuning ; Du, Gang ; Kang, Jinfeng ; Han, Ruqi ; Liu, Xiaoyan
刊名	Japanese Journal of Applied Physics
	2009
DOI	10.1143/JJAP.48.04C052
英文摘要	Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (Tsi) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing T si can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length. ? 2009 The Japan Society of Applied Physics.; EI; 4 PART 2; 48
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/460942]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Yu, Shimeng,Zhao, Yuning,Du, Gang,et al. Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness[J]. Japanese Journal of Applied Physics,2009.
APA	Yu, Shimeng,Zhao, Yuning,Du, Gang,Kang, Jinfeng,Han, Ruqi,&Liu, Xiaoyan.(2009).Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness.Japanese Journal of Applied Physics.
MLA	Yu, Shimeng,et al."Triple-gate fin field effect transistors with fin-thickness optimization to reduce the impact of fin line edge roughness".Japanese Journal of Applied Physics (2009).