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	Quality Evaluation and Simulation of Through-Multilayer TSV Integration Process for Memory Stacking
	Guan, Yang ; Zeng, Qinghua ; Chen, Jing ; Jin, Yufeng ; Ma, Shenglin
	2015
关键词	Through Silicon Via(TSV) Memory Stacking Bonding Strength Thermodynamic Sinmlation
英文摘要	3D integration using through silicon via (TSV) has many advantages, such as high packaging density, small form factor and high bandwidth due to the short connection lengths. In this paper, a through-multilayer integration approach for memory module was proposed with the RDLs being fabricated using lift-off process prior to via filling. The stacking samples containing of 3 layers were prepared and all the 88 dies on the 4-inch wafer were measured. The average resistance of single layer Kelvin test structure was 1.54m Omega, with the lowest and highest measured values being 1.37m Omega and 1.69m Omega respectively. The quality of bonding strength has been characterized through shear tests, and the optimized bonding parameters have been put forward after a set of parameter combinations experiment. The average of shear strength increased by 6.44% after process optimization. The mean of bonding precision was 3.31 mu m, with the bonding yield being 94.17%, which meet the requirements of precision within 5 mu m. Thermodynamic simulation has been done to characterize the Mises stress and warping values of 3 layers TSV integration. All test results supported the good quality of this through-multilayer integration approach.; CPCI-S(ISTP); j.chen@pku.edu.cn
语种	英语
出处	16 int conf elect packaging technology
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/450322]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Guan, Yang,Zeng, Qinghua,Chen, Jing,et al. Quality Evaluation and Simulation of Through-Multilayer TSV Integration Process for Memory Stacking. 2015-01-01.

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