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	Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics
	Wang, Yuan ; Liu, Yuequan ; Jiang, Mengyin ; Jia, Song ; Zhang, Xing
	2016
英文摘要	A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to x4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5~40 cycles to finish locking. ? 2016 IEEE.; EI; 1-4; 2016-July
语种	英语
出处	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
DOI标识	10.1109/ISCAS.2016.7527155
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/449341]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wang, Yuan,Liu, Yuequan,Jiang, Mengyin,et al. Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. 2016-01-01.

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