Fabrication, Characterization, and Simulation of a Low-Cost TSV   Integration Without Front-Side CMP Process

doi:10.1109/TSM.2016.2518707

CORC > 北京大学 > 信息科学技术学院

	Fabrication, Characterization, and Simulation of a Low-Cost TSV Integration Without Front-Side CMP Process
	Guan, Yong ; Zhu, Yunhui ; Ma, Shenglin ; Zeng, Qinghua ; Chen, Jing ; Jin, Yufeng
刊名	IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
	2016
关键词	3D packaging through silicon via memory stacking bonding strength THROUGH-SILICON VIAS 3-D TECHNOLOGY INTERCONNECTS
DOI	10.1109/TSM.2016.2518707
英文摘要	In this paper, a low-cost through-multilayer TSV integration process has been developed. The features are that a double-layer spin coating technique is applied to prevent residual photoresist left inside TSVs. Besides, redistribution layer is deposited before TSV filling in order to eliminate the front-side chemical-mechanical planarization process, which will lower the fabrication cost. Basic electrical tests of single layer chip are performed in order to pick out these known good dies for stacking. A given mass of stacking TSV integration samples are fabricated. Electrical test results are presented to show the quality of TSV interconnects and TSV isolation. The quality of bonding strength is characterized through shear tests, and the optimized bonding parameters are put forward after a set of experiments with different parameter combinations. The mean of bonding precision is 3.31 mu m, with the bonding yield being 94.17%. Thermodynamic simulation is simulated to characterize the stress and warping values of this multi-layers TSV integration. All test results support the good quality of this through-multilayer integration approach.; National Natural Science Foundation of China [U1537208]; Major State Basic Research Development Program of China [2015CB0572]; SCI(E); EI; ARTICLE; guanyong@pku.edu.cn; pkuzyh@pku.edu.cn; mashenglin1983@sina.com; zengqinghua@pku.edu.cn; j.chen@pku.edu.cn; yfjin@pku.edu.cn; 2; 70-78; 29
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/437353]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Guan, Yong,Zhu, Yunhui,Ma, Shenglin,et al. Fabrication, Characterization, and Simulation of a Low-Cost TSV Integration Without Front-Side CMP Process[J]. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING,2016.
APA	Guan, Yong,Zhu, Yunhui,Ma, Shenglin,Zeng, Qinghua,Chen, Jing,&Jin, Yufeng.(2016).Fabrication, Characterization, and Simulation of a Low-Cost TSV Integration Without Front-Side CMP Process.IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING.
MLA	Guan, Yong,et al."Fabrication, Characterization, and Simulation of a Low-Cost TSV Integration Without Front-Side CMP Process".IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING (2016).