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	First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap
	Huang, Qianqian ; Jia, Rundong ; Chen, Cheng ; Zhu, Hao ; Guo, Lingyi ; Wang, Junyao ; Wang, Jiaxin ; Wu, Chunlei ; Wang, Runsheng ; Bu, Weihai ; Kang, Jing ; Wang, Wenbo ; Wu, Hanming ; Lee, Shiuh-Wuu ; Wang, Yangyuan ; Huang, Ru
	2016
英文摘要	We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications. ? 2015 IEEE.; EI; 22.2.1-22.2.4; 2016-February
语种	英语
出处	61st IEEE International Electron Devices Meeting, IEDM 2015
DOI标识	10.1109/IEDM.2015.7409756
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/436300]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Huang, Qianqian,Jia, Rundong,Chen, Cheng,et al. First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap. 2016-01-01.

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