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	A HIGHLY EFFICIENT PIPELINE ARCHITECTURE OF RDO-BASED MODE DECISION DESIGN FOR AVS HD VIDEO ENCODER
	Zhu, Chuang ; Li, Yuan ; Jia, Hui-zhu ; Xie, Xiao-dong ; Yin, Hai-bing
	2011
关键词	mode decision RDO AVS pipeline
英文摘要	Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but with a high computational complexity that limits its applications. In our paper, firstly an MD algorithm based on RDO is given, which makes more mode candidates enter into RDO mode decision with little hardware resource increment. We further analyze the pipeline structure in detail, and implement a block-level 5-stage hardware pipeline. It can support the real time RDO mode decision processing of 1080P@30fps, and the coding efficiency is about 0.5db higher than the traditional SAD method. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18-mu m CMOS technology with 215K logic gates and 80 KB SRAMs.; Computer Science, Hardware & Architecture; Computer Science, Software Engineering; Engineering, Electrical & Electronic; Telecommunications; EI; CPCI-S(ISTP); 0
语种	英语
DOI标识	10.1109/ICME.2011.6011975
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/406284]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhu, Chuang,Li, Yuan,Jia, Hui-zhu,et al. A HIGHLY EFFICIENT PIPELINE ARCHITECTURE OF RDO-BASED MODE DECISION DESIGN FOR AVS HD VIDEO ENCODER. 2011-01-01.

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