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	Process Development of a Stacked Chip Module with TSV Interconnection
	Zhong, Xiao ; Ma, Shenglin ; Zhu, Yunhui ; Bian, Yuan ; Sun, Xin ; Cui, Qinghu ; Miao, Min ; Chen, Jing ; Jin, Yufeng
	2012
关键词	SILICON INTEGRATION
英文摘要	In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a test run is carried out and a four-layer of chip module is demonstrated.; Engineering, Electrical & Electronic; CPCI-S(ISTP); 0
语种	英语
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/405939]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zhong, Xiao,Ma, Shenglin,Zhu, Yunhui,et al. Process Development of a Stacked Chip Module with TSV Interconnection. 2012-01-01.

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