Hardware architecture for AVS entropy encoder

doi:10.1109/TCE.2008.4560159

CORC > 北京大学 > 信息科学技术学院

	Hardware architecture for AVS entropy encoder
	Xu, Long ; Deng, Lei ; Ji, Xiangyang ; Peng, Xiaoming ; Gao, Wen
刊名	ieee transactions on consumer electronics
	2008
关键词	AVS-P2 entropy coding VLC context-based hardware pipeline ALGORITHM
DOI	10.1109/TCE.2008.4560159
英文摘要	In AVS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know, such the serial run-length method is usually undesirable for hardware accelerator and thus, this paper proposes an efficient parallel algorithm to Run-Length Coding, which can determine the (Run, Level) combinations for one row of coefficients from a block in one clock cycle. In addition, Level-based multiple VLC tables switch mechanism (Context-based VLC) is further introduced in AVS-P2 entropy coding module to identify the big variation of probability distribution of (Run, Level) combinations. As a result, table selection for coding the current Level necessarily depends on the previously coded coefficients. Thus, we propose a parallel Looking-Up Table method, which can select the tables for one row of coefficients from a block in one clock cycle. On the other band, at RDO stage, the calculation of rate term only needs to get the number of bits for each coded signal without the knowledge of its concrete value. Consequently, in hardware design, the Looking-Up Table in pre-coding can be mapped into a series of logic operations and thus much hardware memory can be saved. At the actual entropy coding, we only need to replace the logic operation of pre-coding with the actual 2D-VLC tables. Using our proposed hardware accelerator of A VS entropy coder, the results of simulation and synthesis demonstrate that the computing complexity and memory requirements are both reduced.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000257285300085&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Telecommunications; SCI(E); EI; 1; ARTICLE; 2; 769-777; 54
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/397394]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Xu, Long,Deng, Lei,Ji, Xiangyang,et al. Hardware architecture for AVS entropy encoder[J]. ieee transactions on consumer electronics,2008.
APA	Xu, Long,Deng, Lei,Ji, Xiangyang,Peng, Xiaoming,&Gao, Wen.(2008).Hardware architecture for AVS entropy encoder.ieee transactions on consumer electronics.
MLA	Xu, Long,et al."Hardware architecture for AVS entropy encoder".ieee transactions on consumer electronics (2008).