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Performance estimations of gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain
Pu, Jing ; Sun, Lei ; Han, Ru-Qi
2010
英文摘要The performance of n-channel gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain (ASB-SiNW-FET) was simulated. Some impact factors are studied. The results suggest that the drain current and threshold voltage are mainly determined by source-side barrier height (S-SBH). Increasing S-SBH or decreasing nanowire radius can optimize sub-threshold slope, while decreasing S-SBH can enhance the drain current and suppress the fluctuation of threshold voltage. ? 2010 IEEE.; EI; 0
语种英语
DOI标识10.1109/IWJT.2010.5474964
内容类型其他
源URL[http://ir.pku.edu.cn/handle/20.500.11897/295610]  
专题信息科学技术学院
推荐引用方式
GB/T 7714
Pu, Jing,Sun, Lei,Han, Ru-Qi. Performance estimations of gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain. 2010-01-01.
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