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	Design and optimization methodology for 3D RRAM arrays
	Deng, Yexin ; Chen, Hong-Yu ; Gao, Bin ; Yu, Shimeng ; Wu, Shih-Chieh ; Zhao, Liang ; Chen, Bing ; Jiang, Zizhen ; Liu, Xiaoyan ; Hou, Tuo-Hung ; Nishi, Yoshio ; Kang, Jinfeng ; Wong, H.-S. Philip
	2013
英文摘要	3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption. ? 2013 IEEE.; EI; 0
语种	英语
DOI标识	10.1109/IEDM.2013.6724693
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/294419]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Deng, Yexin,Chen, Hong-Yu,Gao, Bin,et al. Design and optimization methodology for 3D RRAM arrays. 2013-01-01.

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