A 6-bit 1 GS/s DAC using an area efficient switching scheme for   gradient-error tolerance

doi:10.1587/elex.10.20130328

CORC > 北京大学 > 信息科学技术学院

	A 6-bit 1 GS/s DAC using an area efficient switching scheme for gradient-error tolerance
	Wang, Haonan ; Yao, Yufeng ; Wang, Tao ; Wang, Hui ; Cheng, Yuhua
刊名	ieice electronics express
	2013
关键词	DAC switching scheme gradient error
DOI	10.1587/elex.10.20130328
英文摘要	This paper presents a 6-bit current-steering DAC fabricated in 65 nm digital CMOS process. In order to compensate for the systematic errors on the current sources, a novel switching scheme is proposed which can theoretically cancel out linear and quadratic gradient errors. Its implementation only requires reasonable number of current sources without increasing in the design complexity. The measured DNL and INL are 0.012 LSB and 0.023 LSB respectively. At the sampling rate of 1 GS/s, 5.9 bit ENOB and 51.4 dB SFDR at Nyquist frequency are achieved.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000321672100010&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; SCI(E); EI; 2; ARTICLE; 11; 1-9; 10
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/291785]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Wang, Haonan,Yao, Yufeng,Wang, Tao,et al. A 6-bit 1 GS/s DAC using an area efficient switching scheme for gradient-error tolerance[J]. ieice electronics express,2013.
APA	Wang, Haonan,Yao, Yufeng,Wang, Tao,Wang, Hui,&Cheng, Yuhua.(2013).A 6-bit 1 GS/s DAC using an area efficient switching scheme for gradient-error tolerance.ieice electronics express.
MLA	Wang, Haonan,et al."A 6-bit 1 GS/s DAC using an area efficient switching scheme for gradient-error tolerance".ieice electronics express (2013).