QQ客服 官方微博 反馈留言

	Design and Implementation for High Speed LDPC Decoder with Layered Decoding
	Ding, Hong ; Yang, Shuai ; Luo, Wu ; Dong, Mingke
	2009
关键词	LDPC layered decoder highspeed PARITY-CHECK CODES FPGA
英文摘要	This paper presents a layered decoding algorithm for LDPC code and analyzes the advantages and challenge for high speed implementation. Simulation result indicates that layered decoding algorithm converge two times faster than traditional decoding algorithm. A new code, construction scheme aimed to design high speed LDPC decoder with layered decoding algorithm is put forward. This code construction method helps to increase the parallel degree of decoder by suffering with little performance loss. Using the layered decoding algorithm and code construction scheme, a length 2304, rate 1/2 LDPC decoder which can achieve about 768 Mbps information throughput has been implemented on FPGA platform.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000265599800032&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Computer Science, Information Systems; Engineering, Electrical & Electronic; Telecommunications; EI; CPCI-S(ISTP); 6
语种	英语
DOI标识	10.1109/CMC.2009.284
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/261005]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Ding, Hong,Yang, Shuai,Luo, Wu,et al. Design and Implementation for High Speed LDPC Decoder with Layered Decoding. 2009-01-01.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。