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A fast two-stage sample-and-hold amplifier for pipelined ADC application
Ruan, Jian ; Lee, Chung Len
2008
关键词sample-and-hold amplifier two-stage structure pipelined ADC bootstrapped switch bottom-plate sampling CMOS
英文摘要This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18um 1.8V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63d8 SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000254291500020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Computer Science, Information Systems; Engineering, Electrical & Electronic; EI; CPCI-S(ISTP); 0
语种英语
DOI标识10.1109/DELTA.2008.58
内容类型其他
源URL[http://ir.pku.edu.cn/handle/20.500.11897/153495]  
专题信息科学技术学院
推荐引用方式
GB/T 7714
Ruan, Jian,Lee, Chung Len. A fast two-stage sample-and-hold amplifier for pipelined ADC application. 2008-01-01.
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