Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around   Cylindrical Silicon Nanowire MOSFETs

doi:10.1109/TED.2011.2162521

CORC > 北京大学 > 信息科学技术学院

	Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs
	Zou, Jibin ; Xu, Qiumin ; Luo, Jieying ; Wang, Runsheng ; Huang, Ru ; Wang, Yangyuan
刊名	ieee电子器件汇刊
	2011
关键词	Modeling parasitic gate capacitance Schwarz-Christoffel mapping silicon nanowire MOSFETs (SNWTs) source/drain extension (SDE) SOURCE/DRAIN UNDERLAP FRINGE CAPACITANCE CARRIER TRANSPORT CMOS DEVICES PERFORMANCE OPTIMIZATION TRANSISTORS TECHNOLOGY INTEGRATION RESISTANCE
DOI	10.1109/TED.2011.2162521
英文摘要	In this paper, an analytical model for parasitic gate capacitances in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3-D architecture of SNWTs with surrounding-gate cylindrical channel and source/drain extension regions is taken into account in the parasitic gate capacitance modeling. The parasitic gate capacitances of the SNWT are divided into four parts: 1) outer fringe capacitance C(of); 2) inner fringe capacitance C(if); 3) overlap capacitance C(ov); and 4) sidewall capacitance C(side). The 3-D capacitance system is calculated by useful methods such as the equivalent transformation and inversion of Schwarz-Christoffel mapping. The obtained model agrees well with the results of 3-D electrostatic numerical simulations. The results show that the proportion of parasitic gate capacitances in the total capacitance is increased in this gate-all-around architecture due to the ultrasmall dimension of the SNWT channel; thus, the proportion of the intrinsic capacitance is reduced. Among the capacitances, C(of) is found to be the largest contributor to the total parasitic gate capacitance in FO1 delay calculation, and C(side) manifests itself as a nonnegligible parasitic capacitance. The developed capacitance model can be easily incorporated into a compact core model of SNWTs for further device/circuit design optimizations with various device parameters.; http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000295100300020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701 ; Engineering, Electrical & Electronic; Physics, Applied; SCI(E); EI; 15; ARTICLE; 10; 3379-3387; 58
语种	英语
内容类型	期刊论文
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/152567]
专题	信息科学技术学院
推荐引用方式 GB/T 7714	Zou, Jibin,Xu, Qiumin,Luo, Jieying,et al. Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs[J]. ieee电子器件汇刊,2011.
APA	Zou, Jibin,Xu, Qiumin,Luo, Jieying,Wang, Runsheng,Huang, Ru,&Wang, Yangyuan.(2011).Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs.ieee电子器件汇刊.
MLA	Zou, Jibin,et al."Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs".ieee电子器件汇刊 (2011).