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	Highly optimized implementation of HEVC decoder for general processors
	Meng, Shengbin ; Duan, Yizhou ; Sun, Jun ; Guo, Zongming
	2014
英文摘要	In this paper, we propose a novel design and optimized implementation of the HEVC decoder. First, a novel decoder prototype with refined decoding workflow and efficient memory management is designed. Then on this basis, a series of single-instruction-multiple-data (SIMD) based algorithms are used to speed up several time-consuming modules in HEVC decoding. Finally, a frame-based parallel framework is applied to exploit the multi-threading technology on multicore processors. With the highly optimized HEVC decoder, decoding speed of 246fps on Intel i7-2400 3.4GHz quad-core processor for 1080p videos and 52fps on ARM Cortex-A9 1.2GHz dual-core processor for 720p videos can be achieved in our experiments.; EI; 0
语种	英语
DOI标识	10.1109/MMSP.2014.6958819
内容类型	其他
源URL	[http://ir.pku.edu.cn/handle/20.500.11897/321428]
专题	计算机科学技术研究所
推荐引用方式 GB/T 7714	Meng, Shengbin,Duan, Yizhou,Sun, Jun,et al. Highly optimized implementation of HEVC decoder for general processors. 2014-01-01.

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