High performance chip design is always a hot topic in integrated circuit (IC) field. Clock design plays a critical role in improving chip performance and affecting power consumption. The regular clock layout has always been the ideal way to improve the timing of results. In this paper, we propose a symmetrical clock tree synthesis algorithm for top-level design, including tree architecture planning, matching, merging and embedding. We also integrate buffer insertion and obstacle processing into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by average 17.2% while using less than average 24.5% capacitance resource compared with other symmetrical clock trees.