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题名	可扩展体系结构与SuperV3高性能处理器设计
作者	邵洋
学位类别	博士
答辩日期	2008-05-30
授予单位	中国科学院声学研究所
授予地点	声学研究所
关键词	可扩展处理器 专用指令集处理器 微处理器体系结构 超长指令字 单指令流多数据流
其他题名	Extensible Architecture and High Performance SuperV3 Processor Design
学位专业	信号与信息处理
中文摘要	以可扩展处理器为中心的SOC设计方法是随着SOC设计日益复杂化出现的一种新的设计方法，和传统的RTL设计相比，可以在处理器效率和灵活性上获得较好的平衡。本文首先分析可扩展处理器的体系结构原型设计，以及支持可扩展体系结构的软件优化方法，接着针对通信和多媒体应用的数据和计算密集型的特点，从指令级、部件级以及协处理器级三个不同耦合层次上设计了FFT增强的可扩展体系结构，并针对第三代移动通信系统中的Turbo译码算法和维特比译码设计了专用扩展指令，达到以较小的设计代价、较短的设计周期获得具有高性能、高吞吐率和高效率的扩展处理器的目的。 专用指令集处理器ASIP是细粒度的可扩展处理器设计的典型代表。本文提出了ASIP指令集扩展算法，候选扩展指令的取舍采用量化分析的方法，使用理论最大加速比代替Amdahl定律作为性能分析公式，并设计指令组合成本公式用于分析候选指令的性能和面积折中。实验证明，本算法能够从复杂的设计空间中搜索出全局性能和面积折中的扩展指令集体系结构ISA，是一种有效解决SOC的应用的多样性和时效性特征的设计方法。 在上述基础上，本文详细描述具有超长指令字VLIW结构和单指令流多数据流SIMD技术的四发射SuperV3浮点处理器的组织结构，重点阐述SuperV3处理器的内核体系结构设计策略以及控制通路的设计，并介绍了采用电子系统级ESL技术对处理器进行行为级指令精确和周期精确建模的工作。超级哈佛结构和对称的功能单元保证了处理器片上高带宽与高计算能力的平衡设计；使用隐式并行编码和定长短向量字技术，实现了子字并行性、数据并行性和指令级并行性；采用动态重调度和非规整的定长指令集编码有效克服了代码膨胀问题；采用静态推断机制结合编译器静态调度解决了控制相关和数据相关问题。 基于VLIW和SIMD技术的高性能SuperV3处理器除了能够更好的支持下一代通信领域应用之外，还可以广泛应用于多媒体数据处理，包括音频视频、二维图像、三维图形等家电产品和网络等应用领域。
英文摘要	Extensible processor-centric SOC design methodology is a new design method that arises with the complex SOC design. Compared with RTL design method, it can achieve a better balance between efficiency and flexibility. In this dissertation, we start from choosing the initial extensible processor architecture and presenting the software optimization to support the extensibility. Considering the characteristics of communication and multimedia applications as high data-flow and computation density, three kinds of FFT hardware accelerators from instruction level, function unit level to co-processor level grain as well as special extensible instructions for Turbo and Viterbi decoding algorithms are introduced to design high performance, high throughput and high efficiency application specific processor with less design effort and shorter design cycle. Application specific instruction-set processor (ASIP) is a typical type of fine grain extensible processor. A general greedy instruction set customization design methodology is proposed in this dissertation. The design algorithm uses two quantified formulas and theoretical maximum speedup instead of Amdahl’s law to select instruction-set extension architecture of optimized performance/area tradeoff from complex design space. Experiment results indicate that this design method can significantly improve performance with little area while keeping design cycle short. The design approach is useful for time-critical and diversiform SOC applications. A high performance 32-bit SuperV3 DSP micro-architecture based on VLIW and SIMD techniques is also presented in this dissertation. We focus on the architecture design especially the control data path. Electrical System Level (ESL) design methodology is used to build the accurate behavior level instruction as well as the cycle model. Many high performance techniques are used in this floating-point DSP. Super Harvard architecture (instead of Harvard architecture) and symmetrical function units are used to balance its bandwidth and processing performance. The implicit parallelized coding and fixed-short-vector algorithm make it support sub-word parallelism, data-level parallelism and instruction-level parallelism. A dynamic rescheduling strategy and non-align fixed-length instruction coding are used to overcome the defects of code redundancy. Static predication and static compiler scheduling are also supported to solve the control dependency and the data dependency. Based on VLIW and SIMD technique, the high-performance floating-point SuperV3 processor can support 3rd generation communication application including Turbo and Viterbi decoding and CDMA algorithm etc., as well as multimedia data processing including audio and video compression, 2-D image processing, 3-D graphics, consumer and network products etc.
语种	中文
公开日期	2011-05-07
页码	139
内容类型	学位论文
源URL	[http://159.226.59.140/handle/311008/338]
专题	声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文
推荐引用方式 GB/T 7714	邵洋. 可扩展体系结构与SuperV3高性能处理器设计[D]. 声学研究所. 中国科学院声学研究所. 2008.

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