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题名	微处理器片上调试技术的研究与设计
作者	金辉
学位类别	博士
答辩日期	2007-06-08
授予单位	中国科学院声学研究所
授予地点	声学研究所
关键词	嵌入式系统 片上调试 JTAG 单指令流多数据流 超长指令字 实时地址跟踪 可重构的调试模块
其他题名	Research and Design of On-Chip Debugging of Microprocessor
学位专业	信号与信息处理
中文摘要	调试是微处理器的开发过程中必不可少的阶段。随着嵌入式系统调试技术的发展，片上调试（On Chip Debugging, OCD）因其不占用目标机上的资源、调试环境和程序最终的运行环境一致以及低成本的优势成为主流调试方法。当前绝大多数微处理器厂商都用JTAG调试端口来实现片上调试逻辑。 本文首先描述了SuperV2微处理器的组织结构，它采用超长指令字（Very Long Instruction Word, VLIW）结构和单指令流多数据流（Single-Instruction flow Multiple-Data flow, SIMD）技术，结合了通用微处理器和数字信号处理器的特点，既可以处理大规模的数据，又可以完成复杂的任务管理。但要扩展SuperV2的应用领域，还需使其具备片上调试的功能。本文基于IEEE 1149.1标准，针对SuperV2微处理器的体系结构，在其内部实现在线仿真（In-Circuit Emulator，ICE）单元，并对SuperV2的部分控制逻辑做相应改动，使得修改后的SuperV2微处理器能支持预设断点、单步执行以及访问处理器内部寄存器和存储单元的调试操作。 由于不同的微处理器之间结构的差异很大，不利于重复使用调试硬件逻辑（即片内ICE），导致额外的人力资源和开发时间的浪费。本文研究了调试逻辑的可重构性，设计了一种具有良好移植性的低成本调试模块，在RTL级经过较少的修改即可与多种不同结构的微处理器核集成，支持片上调试的操作。为了弥补片上调试技术的实时性，本文在这种可重构的调试模块内增加了一个跟踪单元，用于实时地址跟踪，将微处理器的地址信息压缩后送到片外，方便开发人员对微处理器的观察和分析。 对于具有多个微处理器核的片上系统而言，片上调试技术面临新的挑战。本文总结了多核的片上调试操作面临的困难，概述了多核调试结构必须具备的条件。详细讨论了几种已有的调试结构，并针对一种可行的多核调试方法展开深入的研究，分析了它与单核调试软件的兼容性，探讨了在并发多核调试操作时软硬件的协同工作。
英文摘要	Debugging is an inevitable stage during the R&D of microprocessors. With development of debugging techniques of embedded systems, On-Chip Debugging (OCD) is gradually becoming the mainstream for saving target resource, ensuring identical environment between debugging and ultimate running of programs, as well as low cost. Currently most of the microprocessor OEMs implement OCD with JTAG ports. In this dissertation, the organization of SuperV2 microprocessor is described firstly. It features the architecture of Very Long Instruction Word (VLIW) and Single-Instruction flow Multiple-Data flow (SIMD) technique. By combining the characters of general purpose microprocessor and DSP, SuperV2 offers both high performance of digital signal processing and capability of complicated controlling. To extend the field of applications, OCD must be supported in SuperV2. In our approach, an In-Circuit Emulator (ICE) unit is added based on IEEE 1149.1 standard and some modifications on control logic are made, which enables SuperV2 support debugging operations such as setting breakpoints, single-step execution, accessing the registers and memory inside the processor, etc. The reuse of embedded ICE unit is proved to be hard, because the architectures and operating methods vary significantly among different microprocessors. This leads to extra human resource and time of development. By exploiting the reconfigurable characters of the embedded ICE, a reusable low-cost module, which can be easily integrated with microprocessor cores with a few modifications at the register-transfer level (RTL), is developed to support OCD functions. A trace unit is also added to the module to satisfy the need of real-time debugging. The address information inside microprocessor are compressed and sent out of the chip for observation and analysis. As SoCs with multiple microprocessor cores are concerned, the OCD technique faces new challenges. This dissertation reviews the prior work in this domain and investigates the difficulties and requisites for multi-core OCD. An applicable multi-TAP access architecture, as well as the software infrastructure needed to control it, is introduced. Relevant hardware-software co-work for the concurrent multi-core debugging is also discussed.
语种	中文
公开日期	2011-05-07
页码	121
内容类型	学位论文
源URL	[http://159.226.59.140/handle/311008/298]
专题	声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文
推荐引用方式 GB/T 7714	金辉. 微处理器片上调试技术的研究与设计[D]. 声学研究所. 中国科学院声学研究所. 2007.

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