| Design and optimization of LDPC encoder in DTMB transmitter | |
| Yang Shu-wen ; Peng Ke-wu ; Pan Chang-yong | |
| 2010-10-12 ; 2010-10-12 | |
| 关键词 | Practical Theoretical or Mathematical/ digital audio broadcasting digital video broadcasting multimedia communication optimisation parity check codes resource allocation shift registers/ optimization low density parity check code LDPC encoder digital terrestrial multimedia broadcasting DTMB transmitter shift register adder accumulator structure resource utilization/ B6420B Radio and television transmitters B6120B Codes B6210R Multimedia communications B1265B Logic circuits B0260 Optimisation techniques |
| 中文摘要 | In this paper, it is introduced that the hardware implementation and resource utilization of LDPC encoder based on shift register adder accumulator (SRAA) structure in digital terrestrial multimedia broadcasting (DTMB) transmitter. In order to improve the resource utilization, a plan of single-rate optimization and triple-rate combination is proposed. |
| 语种 | 中文 |
| 出版者 | Beijing TV and Audio Engineering Publishing House ; China |
| 内容类型 | 期刊论文 |
| 源URL | [http://hdl.handle.net/123456789/82161]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | Yang Shu-wen,Peng Ke-wu,Pan Chang-yong. Design and optimization of LDPC encoder in DTMB transmitter[J],2010, 2010. |
| APA | Yang Shu-wen,Peng Ke-wu,&Pan Chang-yong.(2010).Design and optimization of LDPC encoder in DTMB transmitter.. |
| MLA | Yang Shu-wen,et al."Design and optimization of LDPC encoder in DTMB transmitter".(2010). |
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