| 基于视频应用的交叉寄存DDPS结构设计 | |
| 吴斯奇 ; 王兴军 ; WU Si-qi ; WANG Xing-jun | |
| 2010-06-09 ; 2010-06-09 | |
| 关键词 | 直接数字周期综合 视频时钟 扭环形移位寄存 交叉寄存 direct digital period synthesis(DDPS) video clock twisted ring shifter cross register TN949.197 |
| 其他题名 | A Cross Register DDPS Design Based on Video Application |
| 中文摘要 | 针对视频系统对时钟多样性的要求,基于DDPS(直接数字周期综合)原理,提出了一种新的电路结构,采用分组交叉寄存控制的方式,对800ps和50ps相位分别进行粗选和细选,加以小数部分累加进位补偿,能够获得相位分辨率50ps,平均周期最大误差0.2ps,综合频率达625MHz的视频时钟输出,改变控制字后在5个时钟周期即可获得综合时钟输出。电路采用SMIC0.18μmP1M4Logic1.8V工艺,面积为0.06mm2,功耗最大约32.8mW,适用于视频处理系统中多时钟产生SoC芯片。; Based on the principle of Direct Digital Period Synthesis(DDPS) for various frequencies requirement of video processing system,a new circuit architecture is proposed.With cross registered controlling,800ps-course and 50ps-fine tuning can achieve 50ps period resolution and 0.2ps maximum average error by using 8-bit fraction carry compensation,output clock can be up to 625MHz,the synthesis clock can be generated within 5 cycles after changing the control word.The DDPS layout is done by Cadence IC Full Custom,SMIC 0.18μm P1M4 Logic technology under 1.8V,the area is about 0.06mm2,with maximum power dissipation of about 32.8mW.This DDPS is proper for video processing system which requires various clocks. |
| 语种 | 中文 ; 中文 |
| 内容类型 | 期刊论文 |
| 源URL | [http://hdl.handle.net/123456789/57043]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | 吴斯奇,王兴军,WU Si-qi,等. 基于视频应用的交叉寄存DDPS结构设计[J],2010, 2010. |
| APA | 吴斯奇,王兴军,WU Si-qi,&WANG Xing-jun.(2010).基于视频应用的交叉寄存DDPS结构设计.. |
| MLA | 吴斯奇,et al."基于视频应用的交叉寄存DDPS结构设计".(2010). |
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