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	Design of a 4 k bit ferroelectric memory
	An Li ; Wei Chao-gang ; Ren Tian-ling
	2010-05-07 ; 2010-05-07
关键词	Practical/ ferroelectric capacitors ferroelectric storage network synthesis random-access storage/ ferroelectric memory FeRAM array circuit design SRAM DRAM circuit simulation working cycle sense amplifier ferroelectric capacitor model 120 ns 5 V/ B1265A Digital circuit design, modelling and testing B1265D Memory circuits B2130 Capacitors B2860F Ferroelectric devices/ time 1.2E-07 s voltage 5.0E+00 V
中文摘要	A 4 k bit (512*8 bit) FeRAM array is designed with 1 mu m design rules developed by Institute of Microelectronics of Tsinghua University. The design method for ferroelectric memory, which is quite different from that of conventional memories, such as SRAM and DRAM, is described in particular in the paper. Simulation results show that the device operates at 5 V power supply with a working cycle of 120 ns.
语种	中文 ; 中文
出版者	Editorial Dept. Microelectronics ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16602]
专题	清华大学
推荐引用方式 GB/T 7714	An Li,Wei Chao-gang,Ren Tian-ling. Design of a 4 k bit ferroelectric memory[J],2010, 2010.
APA	An Li,Wei Chao-gang,&Ren Tian-ling.(2010).Design of a 4 k bit ferroelectric memory..
MLA	An Li,et al."Design of a 4 k bit ferroelectric memory".(2010).

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