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	A highly parallel joint VLSI architecture for transforms in H.264/AVC
	Li, Yu ; He, Yun ; Mei, Shunliang
	2010-05-06 ; 2010-05-06
关键词	adaptive block-size transforms H.264/AVC very large-scale integration (VLSI) design Computer Science, Information Systems Engineering, Electrical & Electronic
中文摘要	In H.264/AVC, the concept of adapting the transform size to the block size of motion-compensated prediction residue has proven to be an important coding tool. This paper presents highly parallel joint circuit architecture for 8x8 and 4x4 adaptive block-size transforms in H.264/AVC. By decomposing the 8x8 transform to basic 4x4 transforms, a unified architecture is designed for both 8x8 and 4x4 transform and the transform datapath can be efficiently reused for six kinds of transforms. i.e., 8x8 forward, 8x8 inverse, 4x4 forward, 4x4 inverse, forward-Hadamard, inverse-Hadamard transforms. Linear shift mapping is applied on the memory buffer to support parallel access both in row and column directions which eliminates the need for a transpose circuit. For reusable and configurable transform data-path, a multiple-stage pipeline is designed to reduce the critical path length and increase throughput. The design is implemented under UMC 0.18 um technology at 200 MHz with 13.651 K logic gates, which can support 1,920x1,088 30 fps H.264/AVC HDTV decoder.
语种	英语 ; 英语
出版者	SPRINGER ; NEW YORK ; 233 SPRING ST, NEW YORK, NY 10013 USA
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/11128]
专题	清华大学
推荐引用方式 GB/T 7714	Li, Yu,He, Yun,Mei, Shunliang. A highly parallel joint VLSI architecture for transforms in H.264/AVC[J],2010, 2010.
APA	Li, Yu,He, Yun,&Mei, Shunliang.(2010).A highly parallel joint VLSI architecture for transforms in H.264/AVC..
MLA	Li, Yu,et al."A highly parallel joint VLSI architecture for transforms in H.264/AVC".(2010).

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