一种基于FPGA的数字锁相放大器的实现方法
于海斌; 曾鹏; 石刚; 荣亮; 赵伟; 叶鼎
2016-02-10
专利国别中国
专利号CN105322903A
专利类型发明
产权排序1
权利人中国科学院沈阳自动化研究所
其他题名Implementation method of digital lock-in amplifier based on FPGA
中文摘要本发明涉及一种基于FPGA的数字锁相放大器的实现方法,包括:正交参考信号发生模块,载波信号合成模块,CIC梳状滤波器模块,FIR低通滤波器模块,CORDIC矢量运算模块。正交参考信号发生模块产生与目标信号同频的单位幅值的正交三角函数SIN和COS波。原始信号与正交参考信号SIN,COS通过载波合成模块进行乘积运算,产生两路载波信号。这两路载波信号各自分别通过CIC梳状滤波器模块进行降频,再通过FIR低通滤波器模块进行滤波处理后,经过CORDIC矢量运算模块进行解调及矢量运算,获得目标信号的幅值和相位。本发明克服了常规数字锁相放大器中单路参考信号相位与目标信号必须同相位这一要求。
是否PCT专利
英文摘要The invention relates to an implementation method of a digital lock-in amplifier based on a field programmable gate array (FPGA). The digital lock-in amplifier comprises an orthogonal reference signal generation module, a carrier signal synthesis module, a CIC comb filter module, an FIR (Far Infrared Ray) low-pass filter module and a CORDIC (Coordinated Rotation Digital Computer) vector calculation module. The orthogonal reference signal generation module is used for generating SIN and COS waves of an orthogonal trigonometric function of unit amplitude in common frequency with a target signal. Product operation is carried out on an original signal and orthogonal reference signals SIN and COS through the carrier synthesis module to generate two paths of carrier signals. Underclocking is carried out on the two paths of carrier signals respectively through the CIC comb filter module, filtering processing is carried out through the FIR low-pass filter module, and then demodulation and vector calculation are carried out through the CORDIC vector calculation module, so that the amplitude and phase of the target signal are obtained. The implementation method overcomes the requirement that the phase of a one-channel reference signal must be the same as that of the target signal in a conventional digital lock-in amplifier.
申请日期2014-08-04
语种中文
专利申请号CN201410380672.X
专利代理沈阳科苑专利商标代理有限公司 21002
内容类型专利
源URL[http://ir.sia.cn/handle/173321/17776]  
专题沈阳自动化研究所_工业控制网络与系统研究室
推荐引用方式
GB/T 7714
于海斌,曾鹏,石刚,等. 一种基于FPGA的数字锁相放大器的实现方法. CN105322903A. 2016-02-10.
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